Ashling* RiscFree* Integrated Development Environment (IDE) for Altera® FPGAs User Guide
ID
730783
Date
4/11/2025
Public
1. About this Document
2. Ashling RiscFree* IDE for Altera® FPGAs
3. Ashling Visual Studio Code Extension for Altera FPGAs
4. Ashling RiscFree* Integrated Development Environment (IDE) for Altera® FPGAs User Guide Archives
5. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Altera® FPGAs User Guide
A. Appendix
2.1. About the RiscFree* IDE for Altera® FPGAs IDE
2.2. Getting Started with the Ashling* RiscFree* IDE for Altera® FPGAs
2.3. Using Ashling* RiscFree* IDE for Altera® FPGAs with Nios® V Processor System
2.4. Using Ashling* RiscFree* IDE for Altera® FPGAs with Arm* Hard Processor System
2.5. Debugging Features with RiscFree* IDE for Altera® FPGAs
2.2.1. Installing RiscFree* IDE for Altera FPGAs
2.2.2. Getting Started with RiscFree* IDE for Altera® FPGAs
2.2.3. Creating the Project
2.2.4. Building the Application
2.2.5. Run and Debug Configurations in the RiscFree* IDE for Altera® FPGAs
2.2.6. Debug Information in the RiscFree* IDE for Altera® FPGAs
2.5.1. Debug Features in RiscFree* IDE
2.5.2. Processor System Debug
2.5.3. Heterogeneous Multicore Debug
2.5.4. Debugging µC/OS-II Application
2.5.5. Debugging FreeRTOS Application
2.5.6. Debugging Zephyr Application
2.5.7. Arm* HPS On-Chip Trace
2.5.8. Debugging the Arm* Linux Kernel
2.5.9. Debugging Target Software in an Intel® Simics Simulator Session
3.1. About the Ashling Visual Studio Code Extension
3.2. Getting Started with Ashling* Visual Studio Code Extension
3.3. Using Ashling* Visual Studio Code Extension with Nios® V Processor System
3.4. Using Ashling* Visual Studio Code Extension with Arm Hard Processor System
3.5. Debugging Features in Ashling* Visual Studio Code Extension
3.3.1. Creating Nios® V Processor BSP using Nios® V Processor BSP Generator
3.3.2. Creating Nios® V Processor Application Project using Nios® V App Generator
3.3.3. Importing Nios® V Processor Project
3.3.4. Building Nios® V Processor Project
3.3.5. Debugging a Nios® V Processor Project
3.3.6. Debugging Tools
1. About this Document
Updated for: |
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Intel® Quartus® Prime Design Suite 25.1 |
This document outlines the Ashling* RiscFree* IDE for Altera® FPGAs in with the Visual Studio Code Extension, focusing on debugging HPS and Nios® V processor applications projects. It details the capabilities and features of both tools, including their interfaces, debugging functionalities, and integration methods. Additionally, the document provides instructions for configuring and utilizing these tools to effectively manage and debug application projects on HPS and Nios® V processors.