1.3. System Description
The following system-level diagram shows how the different modules are connected in this design.
In this setup, for example L = 8, M = 4, and F = 1, the data rate of transceiver lanes is 24.75 Gbps.
The Si5332 OUT1 generates 100 MHz clock to mgmt_clk. Si5345-D-EVB generates two clock frequencies, 375 MHz and 100 MHz. The 375 MHz is supplied to the embedded multiplexer in the Intel Agilex® 7 I-Series F-Tile Demo Board through the J19 SMA port. The output clock of the embedded multiplexer drives the F-Tile transceiver reference clock (refclk_xcvr) and JESD204C Intel® FPGA IP core PLL reference clock (refclk_core). 100 MHz from Si5345-D-EVB is connected to the HMC7044 programmable clock generator present in the AD9081 EVM as the clock input (EXT_HMCREF).
The HCM7044 generates a periodic SYSREF signal of 11.71875 MHz through the FMC Connector.
The JESD204C Intel® FPGA IP is instantiated in Duplex mode but only the receiver path is used.