AN 876: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 F-Tile Devices

ID 728670
Date 11/30/2023
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1.6. Test Results

The following table contains the possible results and their definition.

Table 4.  Results Definition
Result Definition
PASS The Device Under Test (DUT) was observed to exhibit conformant behavior.
PASS with comments The DUT was observed to exhibit conformant behavior. However, an additional explanation of the situation is included (example: due to time limitations, only a portion of the testing was performed).
FAIL The DUT was observed to exhibit non-conformant behavior.
Warning The DUT was observed to exhibit behavior that is not recommended.
Refer to comments From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included.

The following table shows the results for test cases SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, and TL.2 with respective values of L, M, F, data rate, sampling clock, link clock, and SYSREF frequencies.

Table 5.  Result for Test Cases SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, and TL.2
No. L M F S HD E N NP ADC Sampling Clock (MHz) FPGA Device Clock (MHz) FPGA Frame Clock (MHz) FPGA Link Clock (MHz) Lane Rate (Gbps) Result
1 8 4 1 1 0 1 16 16 3000.00 375.00 375.00 375.00 24.75 Pass