1.7. Test Result Comments
In each test case, the RX JESD204C Intel® FPGA IP successfully establishes the sync header alignment, extended multiblock alignment, and until user data phase.
No data integrity issue is observed by the Ramp and PRBS checker for JESD configurations covering all physical lanes, also no cyclic redundancy check (CRC) and command parity error is observed.
During certain power cycles, lane deskew error might appear with the parameter configurations. To avoid this error, the LEMC offset values should be programmed or you can automate this with the calibration sweep procedure. For more information on the legal values of LEMC offset, refer to the RBD Tuning Mechanism topic in the F-Tile JESD204C Intel® FPGA IP User Guide.