F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

ID 720998
Date 12/19/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.3. TX and RX Parallel and Serial Signals

Table 9.  TX and RX Parallel and Serial Interface SignalsRefer to Variables Defining Bits for the Interfacing Ports in Port and Signal Reference for variable definitions.
Signal Name Clocks Domain/Resets Direction Description
tx_parallel_data[80*N*X-1:0

coreclkin

tx_reset[m]

Input Synchronous parallel data bus from FPGA core going through EMIB synchronous data path – some bits are mapped to special functionality.
rx_parallel_data[80*N*X-1:0]

coreclkin

rx_reset[m]

Input Synchronous parallel data bus to FPGA core going through EMIB synchronous data path – some bits are mapped to special functionality.
tx_serial_data[N-1:0] tx_reset[m] Output

TX serial data port.

tx_serial_data_n[N-1:0] tx_reset[m] Output Differential pair for TX serial data port.
rx_serial_data[N-1:0] rx_reset[m] Output

RX serial data port.

rx_serial_data_n[N-1:0] rx_reset[m] Output Differential pair for RX serial data port.