F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

ID 720998
Date 12/19/2022
Public

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Document Table of Contents

3.1. Dynamic Reconfiguration QSF Settings

This section describes the QSF settings required for dynamic reconfiguration to work for the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP.

General QSF Settings

The following table describes the general QSF setting that is required and its use.
Table 23.  Dynamic Reconfiguration QSF Setting for the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP
QSF Settings Description
set_instance_assignment -name IP_COLOCATE F_TILE -from <hpath1> -to <hpath2> -entity <top_level_name>

Associates a Dynamic Reconfiguration Controller with the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP that it is controlling.

The <hpath1> is the hierarchy path of the F-Tile Dynamic Reconfiguration Suite Intel FPGA IP in your design and <hpath2> is the hierarchy path of the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP in your design.

set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL -to <bb_instance_hpath> <clock-port-name>

When you have more than one F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP instance and the instance has the Reconfiguration Clock Source parameter set to external, assign the reconfiguration clock source with this .qsf assignment. This step assigns the master clock for the indicated protocol PHY IPs.

If your design is duplex or TX simplex mode, use the following clock source for the <clock-port-name>: pld_pcs_tx_clk_out1_dcm. If your design is RX simplex mode, use the following clock source for the <clock-port-name>: pld_pcs_rx_clk_out1_dcm

Note: Refer to the Reconfiguration Clock Source parameter description in Parameter Settings: General Tab table for more information.
The following example .qsf assignment illustrates the setting for a design using the F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP:
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_dut|dr_f_0 \
-to dut|directphy_f_dr_0