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1. About the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide Archive
9. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP
3.2. Installing and Licensing Intel® FPGA IPs
3.3. Specifying the IP Core Parameters and Options
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IPs
3.6. Upgrading the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Core
3.7. Integrating Your IP Core in Your Design
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7.1. Register Map
You can access the 32-bit configuration registers via the Avalon® memory-mapped interface as described in Avalon Memory-Mapped Interface Signals.
Address Range | Usage | Register Width | Configuration |
---|---|---|---|
0x400–0x43F | USXGMII | 32 | 10M/100M/1G/2.5G/5G/10G (USXGMII) |
Note: Refer to the F-tile Ethernet Hard IP User Guide and F-tile Architecture and PMA and FEC Direct PHY IP User Guide for register map of Ethernet and Transceiver Reconfiguration Interfaces.
Access | Definition |
---|---|
RO | Read only. |
RW | Read and write. |
RWC | Read, write, and clear. The user application writes 1 to the register bit(s) to invoke a defined instruction. The IP core clears the bit(s) upon executing the instruction. |
Observe the following guidelines when accessing the registers:
- Do not write to reserved or undefined registers.
- When writing to the registers, perform read-modify-write operation to ensure that reserved or undefined register bits are not overwritten.