F-Tile Ethernet Multirate Intel® FPGA IP User Guide

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ID 714307
Date 2/01/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide
1. Introduction x
1.1. Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation 1.7. F-Tile Ethernet Multirate IP Core Features and Constraints 1.8. F-Tile Ethernet Multirate IP Core Concepts
1.8. F-Tile Ethernet Multirate IP Core Concepts x
1.8.1. Reconfiguration Group 1.8.2. Base Profile 1.8.3. Secondary Profile 1.8.4. Secondary Profile Group 1.8.5. Startup Profile 1.8.6. Supported Reconfiguration Groups 1.8.7. PTP Timestamp Accuracy Support 1.8.8. Transceiver Lane Mapping
2. Interface Overview x
2.1. Port Numbering Scheme 2.2. Clock Signals 2.3. Reset Signals 2.4. Fractured MAC Segmented Interface for FGT Transceivers 2.5. Fractured MAC Segmented Interface for FHT Transceivers 2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers 2.7. Fractured MAC Avalon ST Client Interface for FHT Transceivers 2.8. Fractured MII PCS-Only Interface for FGT Transceivers 2.9. Fractured MII PCS-Only Interface for FHT Transceivers 2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers 2.11. Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers 2.12. MAC Flow Control Interface 2.13. Status Interface 2.14. Avalon® Memory-Mapped Reconfiguration Interfaces 2.15. Auto-Negotiation and Link Training Interface 2.16. Precision Time Protocol Interface
2.16. Precision Time Protocol Interface x
2.16.1. PTP Clock Interface 2.16.2. Time-of-Day Interface 2.16.3. TX 2-Step Timestamp Interface 2.16.4. TX 1-Step Timestamp Interface 2.16.5. RX Timestamp Interface 2.16.6. PTP Status Interface 2.16.7. PTP Tile Interface
4. Designing with the IP Core x
4.1. Specifying the IP Core Parameters and Options 4.2. Generated File Structure
4.1. Specifying the IP Core Parameters and Options x
4.1.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Precision Time Protocol
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide

2.14. Avalon® Memory-Mapped Reconfiguration Interfaces

The F-Tile Ethernet Multirate IP core supports these Avalon® memory-mapped interfaces:
  • Ethernet reconfiguration Avalon® memory-mapped interface access the hard and soft IP CSRs. Each port instantiates one interface.
  • Transceiver reconfiguration Avalon® memory-mapped interface accesses the transceiver registers. Each transceiver lane instantiates one interface.
The table depicts the interface for different numbers of ports.
Table 65.  Signals of the Ethernet Reconfiguration Avalon® Memory-Mapped Interface For signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Number of Ports Signal Name
1

Port 0:

i_p0_reconfig_eth_addr[13:0]

i_p0_reconfig_eth_read

i_p0_reconfig_eth_write

i_p0_reconfig_eth_byteenable[3:0]

o_p0_reconfig_eth_readdata[31:0]

o_p0_reconfig_eth_readdata_valid

i_p0_reconfig_eth_writedata[31:0]

o_p0_reconfig_eth_waitrequest

2

Port 0:

i_p0_reconfig_eth_addr[13:0]

i_p0_reconfig_eth_read

i_p0_reconfig_eth_write

i_p0_reconfig_eth_byteenable[3:0]

o_p0_reconfig_eth_readdata[31:0]

o_p0_reconfig_eth_readdata_valid

i_p0_reconfig_eth_writedata[31:0]

o_p0_reconfig_eth_waitrequest

Port 1:

i_p1_reconfig_eth_addr[13:0]

i_p1_reconfig_eth_read

i_p1_reconfig_eth_write

i_p1_reconfig_eth_byteenable[3:0]

o_p1_reconfig_eth_readdata[31:0]

o_p1_reconfig_eth_readdata_valid

i_p1_reconfig_eth_writedata[31:0]

o_p1_reconfig_eth_waitrequest

4

Port 0:

i_p0_reconfig_eth_addr[13:0]

i_p0_reconfig_eth_read

i_p0_reconfig_eth_write

i_p0_reconfig_eth_byteenable[3:0]

o_p0_reconfig_eth_readdata[31:0]

o_p0_reconfig_eth_readdata_valid

i_p0_reconfig_eth_writedata[31:0]

o_p0_reconfig_eth_waitrequest

Port 1:

i_p1_reconfig_eth_addr[13:0]

i_p1_reconfig_eth_read

i_p1_reconfig_eth_write

i_p1_reconfig_eth_byteenable[3:0]

o_p1_reconfig_eth_readdata[31:0]

o_p1_reconfig_eth_readdata_valid

i_p1_reconfig_eth_writedata[31:0]

o_p1_reconfig_eth_waitrequest

Port 2:

i_p2_reconfig_eth_addr[13:0]

i_p2_reconfig_eth_read

i_p2_reconfig_eth_write

i_p2_reconfig_eth_byteenable[3:0]

o_p2_reconfig_eth_readdata[31:0]

o_p2_reconfig_eth_readdata_valid

i_p2_reconfig_eth_writedata[31:0]

o_p2_reconfig_eth_waitrequest

Port 3:

i_p3_reconfig_eth_addr[13:0]

i_p3_reconfig_eth_read

i_p3_reconfig_eth_write

i_p3_reconfig_eth_byteenable[3:0]

o_p3_reconfig_eth_readdata[31:0]

o_p3_reconfig_eth_readdata_valid

i_p3_reconfig_eth_writedata[31:0]

o_p3_reconfig_eth_waitrequest

For information about the transceiver reconfiguration Avalon® memory-mapped interface, refer to the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide.

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