6. Configuration Registers
You can access the registers for the F-Tile Ethernet Multirate Intel FPGA IP core using the Avalon® memory-mapped interface or the Ethernet reconfiguration Avalon® memory-mapped interface.
The control status register (CSR) space of all ports is always accessible regardless of whether the port is active. The dynamic reconfiguration (DR)-related registers are used for switching profiles within a reconfiguration group. The DR registers are only available in the port 0 CSR space.
Note:
- In a multiple port profile, the port 0 Avalon® memory-mapped interface space is available even if the port 0 is in reset. This is due to the fact that the i_reconfig_reset signal is a common reset for the entire F-Tile Ethernet Multirate IP core.
- The physical Avalon Memory-Mapped Interface(AVMM) is based on 32-bit word addresses. However, this document refers to the registers as byte addresses, you can convert to word addresses by shifting 2 bits to the right (divide by 4). You can use a byte enabled signal to address individual byes.
The table describes F-Tile Ethernet Multirate IP core specific registers. The F-tile Ethernet Multirate IP core specific registers are all "Read-Write" capable. Refer to F-Tile Ethernet Intel® FPGA Hard IP User Guide for a description of additional Ethernet-related registers.
| Offset (Byte) | Name | Description | Default Setting | |
|---|---|---|---|---|
| 0x200 9 | profile_sel[5:0] | Profile Selection Register
profile_sel[5:0] = {profile_sel[5:4], profile_sel[3:2], profile_sel[1:0]}, where
The profile_sel signal decoding is internally based on the selected reconfiguration group: Signal decoding for the FGT Transceivers:
Signal decoding for the FHT transceivers:
|
Startup Profile | |
| 0x204 | fec_mode[11:0] | FEC Mode Register
fec_mode[11:0] = {fec_mode[11:9], fec_mode[8:6], fec_mode[5:3], fec_mode[2:0]}, where
Selects the FEC type for the active ports in the selected profile:
The port-specific bits only apply to the active ports in the selected profile.
|
FEC mode at startup | |
| 0x208 | sel_25g_10g[3:0] | 10GE/25GE Selection Register: Selects the 10GE or 25GE mode for the active ports in the selected profile. The port-specific bits only apply to the active ports in the selected profile.
The bit definitions are shown below:
Note that the port specific bits only apply to the active ports in the selected profile
This register is applicable only to the following profiles in FGT Reconfiguration Groups:
This register is not applicable to any FHT reconfiguration groups as FHT does not support 10GE rates. |
10GE Enable at startup | |
| 0x20C | preamble_passthrough[3:0] | Preamble Passthrough Enable Register: Enable/Disable preamble passthrough for the active ports in the selected profile.
The bit definitions are shown as below:
Note that the port specific bits only apply to the active ports in the selected profile. This register is applicable only to the following profiles in FGT and FHT Reconfiguration Groups when user interface is set to MAC Avalon ST.
The register default value preamble passthrough is disabled for all other profiles, reconfiguration groups, and user interfaces. |
Preamble Passthrough Enable at Startup | |
9 This offset is only available in port 0 of the Ethernet reconfiguration Avalon® memory-mapped interface space.
10 For 10GE/25GE rate selection, use the 0x208 offset.