F-Tile Ethernet Multirate Intel® FPGA IP User Guide

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ID 714307
Date 4/04/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide
1. Introduction x
1.1. Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation 1.7. F-Tile Ethernet Multirate IP Core Features and Constraints 1.8. F-Tile Ethernet Multirate IP Core Concepts
1.8. F-Tile Ethernet Multirate IP Core Concepts x
1.8.1. Reconfiguration Group 1.8.2. Base Profile 1.8.3. Secondary Profile 1.8.4. Secondary Profile Group 1.8.5. Startup Profile 1.8.6. Supported Reconfiguration Groups 1.8.7. Transceiver Lane Mapping
2. Interface Overview x
2.1. Port Numbering Scheme 2.2. Clock Signals 2.3. Reset Signals 2.4. Fractured MAC Segmented Interface for FGT Transceivers 2.5. Fractured MII or PCS-Only Interface for FGT Transceivers 2.6. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers 2.7. MAC Flow Control Interface 2.8. Status Interface 2.9. Avalon® Memory-Mapped Reconfiguration Interfaces 2.10. Precision Time Protocol Interface
2.10. Precision Time Protocol Interface x
2.10.1. Time-of-Day Interface 2.10.2. TX 2-Step Timestamp Interface 2.10.3. TX 1-Step Timestamp Interface 2.10.4. RX Timestamp Interface 2.10.5. PTP Status Interface 2.10.6. PTP Tile Interface
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Precision Time Protocol
5.1. Precision Time Protocol x
5.1.1. Clocking PTP Timestamp Accuracy
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide

1.8.6. Supported Reconfiguration Groups

This section specifies the supported reconfiguration groups for FGT transceivers.
Table 6.  Available Reconfiguration Groups for FGT Transceivers
Reconfiguration Group Maximum Number of Lanes Modulation System PLL Frequency (in MHz) Supported Profiles 4 Supported FEC Types
25GE-1 Reconfigurable 1 NRZ 806/830 1x25GE-1
  • None
  • IEEE 802.3 BASE-R Firecode (CL74)
  • IEEE 802.3 RS(528,514) (CL91)
  • IEEE 802.3 RS(544,514) (CL134)1 2
1x10GE-1
  • None
50GE-1 Reconfigurable 1 NRZ/PAM4 830 1x50GE-1
  • IEEE 802.3 RS(544,514) (CL134)
  • Ethernet Technology Consortium RS(272, 258)
1x25GE-1
  • None
  • IEEE 802.3 BASE-R Firecode (CL74)
  • IEEE 802.3 RS(528,514) (CL91)
  • IEEE 802.3 RS(544,514) (CL134) 1 2
1x10GE-1
  • None
100GE-4 Reconfigurable 4 NRZ/PAM4 830 1x100GE-4
  • None
  • IEEE 802.3 RS(528,514) (CL91)
  • IEEE 802.3 RS(544,514) (CL134)
1x40GE-4
  • None
2x50GE-2
  • None
  • IEEE 802.3 RS(528,514) (CL91)
  • IEEE 802.3 RS(544,514) (CL134)
1x100GE-2
  • IEEE 802.3 RS(544,514) (CL134)
  • Ethernet Technology Consortium RS(272, 258)
4x25GE-1
  • None
  • IEEE 802.3 BASE-R Firecode (CL74)
  • IEEE 802.3 RS(528,514) (CL91)
  • IEEE 802.3 RS(544,514) (CL134) 1 2
4x10GE-1
  • None
2x50GE-1
  • IEEE 802.3 RS(544,514) (CL134)
  • Ethernet Technology Consortium RS(272, 258)
100GE-2 Reconfigurable3 2 NRZ/PAM4 830 1x100GE-2
  • IEEE 802.3 RS(544,514) (CL134)
  • Ethernet Technology Consortium RS(272, 258)
2x50GE-1
  • IEEE 802.3 RS(544,514) (CL134)
  • Ethernet Technology Consortium RS(272, 258)
2x25GE-1
  • None
  • IEEE 802.3 BASE-R Firecode (CL74)
  • IEEE 802.3 RS(528,514) (CL91)
  • IEEE 802.3 RS(544,514) (CL134) 1 2
2x10GE-1
  • None
1x50GE-2
  • None
  • IEEE 802.3 RS(528,514) (CL91)
  • IEEE 802.3 RS(544,514) (CL134)
400GE-8 Reconfigurable 8 PAM4 830 1x400GE-8
  • IEEE 802.3 RS(544,514) (CL134)
  • Ethernet Technology Consortium RS(272, 258)
2x200GE-4
  • IEEE 802.3 RS(544,514) (CL134)
  • Ethernet Technology Consortium RS(272, 258)
4x100GE-2
  • IEEE 802.3 RS(544,514) (CL134)
  • Ethernet Technology Consortium RS(272, 258)
200GE-4 Reconfigurable3 4 NRZ/PAM4 830 1x200GE-4
  • IEEE 802.3 RS(544,514) (CL134)
  • Ethernet Technology Consortium RS(272, 258)
2x100GE-2
  • IEEE 802.3 RS(544,514) (CL134)
  • Ethernet Technology Consortium RS(272, 258)
1x100GE-4
  • None
  • IEEE 802.3 RS(528,514) (CL91)
  • IEEE 802.3 RS(544,514) (CL134)
2x50GE-2
  • None
  • IEEE 802.3 RS(528,514) (CL91)
  • IEEE 802.3 RS(544,514) (CL134)
4x50GE-1
  • IEEE 802.3 RS(544,514) (CL134)
  • Ethernet Technology Consortium RS(272, 258)
1 Applicable for System PLL rate of 830 MHz frequency, and for MAC and PCS client interface.
2 PTP feature is not available for this RS-FEC configuration.
3 PTP feature is not available for this reconfiguration group.
4 The highlighted profile is the group's base profile.
Level Two Title