Visible to Intel only — GUID: zft1643389685688
Ixiasoft
2.1. Port Numbering Scheme
2.2. Clock Signals
2.3. Reset Signals
2.4. Fractured MAC Segmented Interface for FGT Transceivers
2.5. Fractured MII or PCS-Only Interface for FGT Transceivers
2.6. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers
2.7. MAC Flow Control Interface
2.8. Status Interface
2.9. Avalon® Memory-Mapped Reconfiguration Interfaces
2.10. Precision Time Protocol Interface
Visible to Intel only — GUID: zft1643389685688
Ixiasoft
2. Interface Overview
This section describes various interfaces of the F-Tile Ethernet Multirate Intel FPGA IP core.
Figure 2. F-Tile Ethernet Multirate IP Core Interface Diagram
- Port Numbering Scheme
- Clock Signals
- Reset Signals
- Fractured MAC Segmented Interface for FGT Transceivers
- Fractured MII or PCS-Only Interface for FGT Transceivers
- Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers
- MAC Flow Control Interface
- Status Interface
- Avalon Memory-Mapped Reconfiguration Interfaces
- Precision Time Protocol Interface