F-Tile Ethernet Multirate Intel® FPGA IP User Guide

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ID 714307
Date 4/04/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide
1. Introduction x
1.1. Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation 1.7. F-Tile Ethernet Multirate IP Core Features and Constraints 1.8. F-Tile Ethernet Multirate IP Core Concepts
1.8. F-Tile Ethernet Multirate IP Core Concepts x
1.8.1. Reconfiguration Group 1.8.2. Base Profile 1.8.3. Secondary Profile 1.8.4. Secondary Profile Group 1.8.5. Startup Profile 1.8.6. Supported Reconfiguration Groups 1.8.7. Transceiver Lane Mapping
2. Interface Overview x
2.1. Port Numbering Scheme 2.2. Clock Signals 2.3. Reset Signals 2.4. Fractured MAC Segmented Interface for FGT Transceivers 2.5. Fractured MII or PCS-Only Interface for FGT Transceivers 2.6. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers 2.7. MAC Flow Control Interface 2.8. Status Interface 2.9. Avalon® Memory-Mapped Reconfiguration Interfaces 2.10. Precision Time Protocol Interface
2.10. Precision Time Protocol Interface x
2.10.1. Time-of-Day Interface 2.10.2. TX 2-Step Timestamp Interface 2.10.3. TX 1-Step Timestamp Interface 2.10.4. RX Timestamp Interface 2.10.5. PTP Status Interface 2.10.6. PTP Tile Interface
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Precision Time Protocol
5.1. Precision Time Protocol x
5.1.1. Clocking PTP Timestamp Accuracy
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide

2.10.4. RX Timestamp Interface

A separate RX timestamp interface is available for each supported port within a reconfiguration group.

For 400GE rate, width of TX 2-step timestamp is 2x of other Ethernet rates. The interface signals of port 2 and port 0 are concatenated for 400GE port 0 usage as below: 
{msb, lsb} == {o_p2_ptp_<signals>, o_p0_ptp_<signals>}
The below table shows the interface details for different number of ports.
Table 40.  Signals of the RX Timestamp InterfaceFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Maximum Number of Ports Applicable Reconfiguration Groups Signal Name
1

25GE-1 Reconfigurable

50GE-1 Reconfigurable

Port 0:

o_p0_ptp_rx_its[95:0]

o_p0_ptp_rx_its_valid

o_p0_ptp_rx_its_vl[4:0]

2

100GE-2 Reconfigurable

Port 0:

o_p0_ptp_rx_its[95:0]

o_p0_ptp_rx_its_valid

o_p0_ptp_rx_its_vl[4:0]

Port 1:

o_p1_ptp_rx_its[95:0]

o_p1_ptp_rx_its_valid

o_p1_ptp_rx_its_vl[4:0]

4

100GE-4 Reconfigurable

400GE-8 Reconfigurable

200GE-4 Reconfigurable

Port 0:

o_p0_ptp_rx_its[95:0]

o_p0_ptp_rx_its_valid

o_p0_ptp_rx_its_vl[4:0]

Port 1:

o_p1_ptp_rx_its[95:0]

o_p1_ptp_rx_its_valid

o_p1_ptp_rx_its_vl[4:0]

Port 2:

o_p2_ptp_rx_its[95:0]

o_p2_ptp_rx_its_valid

o_p2_ptp_rx_its_vl[4:0]

Port 3:

o_p3_ptp_rx_its[95:0]

o_p3_ptp_rx_its_valid

o_p3_ptp_rx_its_vl[4:0]

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