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2.1. Port Numbering Scheme
2.2. Clock Signals
2.3. Reset Signals
2.4. Fractured MAC Segmented Interface for FGT Transceivers
2.5. Fractured MII or PCS-Only Interface for FGT Transceivers
2.6. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers
2.7. MAC Flow Control Interface
2.8. Status Interface
2.9. Avalon® Memory-Mapped Reconfiguration Interfaces
2.10. Precision Time Protocol Interface
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7. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide
Document Version | Intel® Quartus® Prime Version | IP Version | Changes |
---|---|---|---|
2022.04.04 | 22.1 | 2.0.0 | Initial release. |