Symmetric Cryptographic Intel FPGA Hard IP User Guide

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ID 714305
Date 12/19/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Cryptographic IP Data Profiles 7. Configuration Registers 8. Design Example 9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives 10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
1. Introduction x
1.1. Terminology 1.2. IP Core Overview 1.3. Release Information 1.4. Device Family Support 1.5. Resource Utilization
1.2. IP Core Overview x
1.2.1. IP Core Applications
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. AXI-ST Interface 2.4. AXI-Lite Interface
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Symmetric Cryptographic IP Core Flow 4.5. Dynamically Disabling SM4 Capability 4.6. Error Handling 4.7. Error Reporting 4.8. Resetting the IP Core 4.9. Channel Definition and Allocation 4.10. Byte Ordering 4.11. AXI-ST Single Packet Mode 4.12. AXI-ST Multiple Packet Mode
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.6. Error Handling x
4.6.1. Detected Error Handling 4.6.2. Key RAM ECC Error Handling
5. Block Description x
5.1. Reset Sequencer 5.2. AXI-ST Ready Latency 5.3. AXI Adapter 5.4. Integrity Check Value Comparison 5.5. GCM Padding and Depadding
5.3. AXI Adapter x
5.3.1. MAC Packing 5.3.2. Data Last Indicator 5.3.3. Stream and Channel ID Buffering 5.3.4. TKEEP and LAST_SEGMENT Signals Generation 5.3.5. MAC Dropping on Decryption
5.5. GCM Padding and Depadding x
5.5.1. GCM Padding 5.5.2. GCM Depadding
6. Cryptographic IP Data Profiles x
6.1. MAC Security Profile (MACsec) 6.2. IP Security Profile (IPsec) 6.3. Generic GCM Profile (GCM) 6.4. Generic XTS Profile (XTS)
6.1. MAC Security Profile (MACsec) x
6.1.1. MACsec Flow 6.1.2. AXI-ST Interface Using MAC Security (MACsec) Profile Pattern
6.2. IP Security Profile (IPsec) x
6.2.1. AXI-ST Interface Using IP Security (IPsec) Profile Pattern
6.3. Generic GCM Profile (GCM) x
6.3.1. AXI- ST Interface Using Generic GCM Profile Pattern
6.4. Generic XTS Profile (XTS) x
6.4.1. AXI-ST Interface Using Generic XTS Profile Pattern
7. Configuration Registers x
7.1. Cryptographic Primary Control Register 7.2. Cryptographic Secondary Control Register 7.3. Cryptographic Primary Status Register 7.4. Cryptographic Error Status Register 7.5. Cryptographic Error Control Register 7.6. Cryptographic Packet Error Control 1 Register 7.7. Cryptographic Packet Error Control 2 Register 7.8. Cryptographic Error Code Control 1 Register 7.9. Cryptographic Error Code Control 2 Register 7.10. Cryptographic Error Code Internal Control Register 7.11. Cryptographic Internal Error Control Register 7.12. Cryptographic First Error Log Register 7.13. Cryptographic Packet Error Log 1 Register 7.14. Cryptographic Packet Error Log 2 Register 7.15. Cryptographic Internal Error Log Register 7.16. Cryptographic Wall Clock LSB Register 7.17. Cryptographic Wall Clock MSB Register 7.18. Ternary Control Register
8. Design Example x
8.1. Functional Description 8.2. Crypto VSIP Top Block Descriptions 8.3. Test Configurations 8.4. Software Requirements 8.5. Simulation Requirements 8.6. Steps to Generate the Design Example 8.7. Running Simulation Tests 8.8. Running Hardware Tests
8.2. Crypto VSIP Top Block Descriptions x
8.2.1. Clock and Reset 8.2.2. Host Interface
8.7. Running Simulation Tests x
8.7.1. Steps to Simulate the Design Example
8.8. Running Hardware Tests x
8.8.1. Supported Boards 8.8.2. Steps to Compile the Design Example for Hardware 8.8.3. Steps to Run the Design Example on Hardware
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide

7.1. Cryptographic Primary Control Register

Table 44.   ctrl_primary Register
Offset 0x00
Addressing Mode 32-bits
Description Cryptographic primary control register.
Table 45.   ctrl_primary Field Description
Bit Name Type Reset Description
31 cif_err_rd_ena RW 0x1 Enables the status error register reading.

The error status registers use the i_crypto_clk clock domain and the sector_reset domain.

To access the error status registers when i_crypto_clk is not available or when the sector_reset is asserted, you unset the cif_err_rd_ena signal bit.

30 Reserved
29 clear_all_status_registers RW 0x1 When set, clears all status registers.
28 clear_error_register RW 0x1 When set, clears the error status register.
27:24 Reserved
23:20 axi_st0_latency RW 0x7 AXI-ST Latency for the first 256-bits AXI-ST Interface

Specifies the number of additional pipeline stage between the AXI-ST initiator and a target.

19:16 axi_lite_latency RW 0x7 AXI Lite Latency

Specifies the number of additional pipeline stage between the AXI Lite initiator and a target.

15 Reserved
14 wallcounter_reset RW 0x0 Resets the wall clock counter.
13 ccf_clk_en RW 0x0 CCL Clock gate enable

When set,

12 cif_clk_en RW 0x0  
11 clear_ipsec_bridge_states RW 0x0 When set, clears the IP SEC bridge packetizer and depacketizer states.
10 clear_macsec_bridge_states RW 0x0 When set, clears the IP MACSEC bridge packetizer and depacketizer states.
9 clear_xts_bridge_states RW 0x0 When set, clears the GCM bridge packetizer and depacketizer states.
8 clear_gcm_bridge_states RW 0x0 When set, clears the GCM bridge packetizer and depacketizer states.
7 xts_disable_type RW 0x0
6 cts_disable_type RW 0x0
5:4 Reserved
3 axi_data_width_type RW 0x0 When set, the AXI interface width is 2x256. Otherwise, the AXI width is 1x512.
2 sm4_disable_type RW 0x0 When set, disables the cryptographic engine for the SM4 algorithm and forces the cryptographic IP to only operate in the AES mode.

If AXI-ST ingress packet includes the AES tuser bit, error detection asserts on egress port during the data cycle. The sm4_disable_type is forced on when fmica_fuse_disable_sm4 is set.

1 aes_disable_type RW 0x0 When set, disables the cryptographic engine for the AES algorithm and forces the cryptographic IP to only operate in the SM4 mode.

If AXI-ST ingress packet includes the AES tuser bit, error detection asserts on egress port during the data cycle. The sm4_disable_type is forced on when fmica_fuse_disable_aes is set.

0 crypto_disable_type RW 0 When set, disables the cryptographic engine for the AES and SM4 algorithms by asserting ccl_reset signal and gating-off the i_crypto_clk clock.

If fmica_fuse_disable_aes and fmica_fuse_disable_sm4 are set, it forces to set the crypto_disable_type signal.

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