Symmetric Cryptographic Intel FPGA Hard IP User Guide

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ID 714305
Date 12/19/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Cryptographic IP Data Profiles 7. Configuration Registers 8. Design Example 9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives 10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
1. Introduction x
1.1. Terminology 1.2. IP Core Overview 1.3. Release Information 1.4. Device Family Support 1.5. Resource Utilization
1.2. IP Core Overview x
1.2.1. IP Core Applications
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. AXI-ST Interface 2.4. AXI-Lite Interface
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Symmetric Cryptographic IP Core Flow 4.5. Dynamically Disabling SM4 Capability 4.6. Error Handling 4.7. Error Reporting 4.8. Resetting the IP Core 4.9. Channel Definition and Allocation 4.10. Byte Ordering 4.11. AXI-ST Single Packet Mode 4.12. AXI-ST Multiple Packet Mode
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.6. Error Handling x
4.6.1. Detected Error Handling 4.6.2. Key RAM ECC Error Handling
5. Block Description x
5.1. Reset Sequencer 5.2. AXI-ST Ready Latency 5.3. AXI Adapter 5.4. Integrity Check Value Comparison 5.5. GCM Padding and Depadding
5.3. AXI Adapter x
5.3.1. MAC Packing 5.3.2. Data Last Indicator 5.3.3. Stream and Channel ID Buffering 5.3.4. TKEEP and LAST_SEGMENT Signals Generation 5.3.5. MAC Dropping on Decryption
5.5. GCM Padding and Depadding x
5.5.1. GCM Padding 5.5.2. GCM Depadding
6. Cryptographic IP Data Profiles x
6.1. MAC Security Profile (MACsec) 6.2. IP Security Profile (IPsec) 6.3. Generic GCM Profile (GCM) 6.4. Generic XTS Profile (XTS)
6.1. MAC Security Profile (MACsec) x
6.1.1. MACsec Flow 6.1.2. AXI-ST Interface Using MAC Security (MACsec) Profile Pattern
6.2. IP Security Profile (IPsec) x
6.2.1. AXI-ST Interface Using IP Security (IPsec) Profile Pattern
6.3. Generic GCM Profile (GCM) x
6.3.1. AXI- ST Interface Using Generic GCM Profile Pattern
6.4. Generic XTS Profile (XTS) x
6.4.1. AXI-ST Interface Using Generic XTS Profile Pattern
7. Configuration Registers x
7.1. Cryptographic Primary Control Register 7.2. Cryptographic Secondary Control Register 7.3. Cryptographic Primary Status Register 7.4. Cryptographic Error Status Register 7.5. Cryptographic Error Control Register 7.6. Cryptographic Packet Error Control 1 Register 7.7. Cryptographic Packet Error Control 2 Register 7.8. Cryptographic Error Code Control 1 Register 7.9. Cryptographic Error Code Control 2 Register 7.10. Cryptographic Error Code Internal Control Register 7.11. Cryptographic Internal Error Control Register 7.12. Cryptographic First Error Log Register 7.13. Cryptographic Packet Error Log 1 Register 7.14. Cryptographic Packet Error Log 2 Register 7.15. Cryptographic Internal Error Log Register 7.16. Cryptographic Wall Clock LSB Register 7.17. Cryptographic Wall Clock MSB Register 7.18. Ternary Control Register
8. Design Example x
8.1. Functional Description 8.2. Crypto VSIP Top Block Descriptions 8.3. Test Configurations 8.4. Software Requirements 8.5. Simulation Requirements 8.6. Steps to Generate the Design Example 8.7. Running Simulation Tests 8.8. Running Hardware Tests
8.2. Crypto VSIP Top Block Descriptions x
8.2.1. Clock and Reset 8.2.2. Host Interface
8.7. Running Simulation Tests x
8.7.1. Steps to Simulate the Design Example
8.8. Running Hardware Tests x
8.8.1. Supported Boards 8.8.2. Steps to Compile the Design Example for Hardware 8.8.3. Steps to Run the Design Example on Hardware
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide

7.15. Cryptographic Internal Error Log Register

Table 72.   interr_log Register
Offset 0x4C
Addressing Mode 32-bits
Description Cryptographic error log register.
Table 73.   interr_log Field Description
Bit Name Type Reset Description
31   RO 0x0 Pack Macsec: UNC ECC -- Macsec Pack RAM Unc ECC consumed by Bridge. Bridge is unreliable. User should reset the bridge.
30   RO 0x0 Pack Macsec: Macsec SM is in ERROR state. Requires error_clear to recover. May get here due to: - Corrupted 'state' info in RAM - unexpected total_num_bytes value (should be unreachable). - Missing SOP (Got data/eop without SOP) - Missing EOP (Got SOP without EOP) NOTE: While in ERROR state, Macsec forwards data cycles to AXI-ST as-is.
29   RO 0x0 Pack Macsec: Protocol Err -- Got SOP/EOP error that was not flagged by Depacketizer. Or Got runt that requires 2 EOPs, or 2 SOPs to be forwarded on AXIST.
28   RO 0x0 Depack Macsec: Unc ECC -- Macsec Unpack RAM had Unc ECC that was consumed by Bridge. Bridge is unreliable. User should reset the bridge.
27   RO 0x0 Depack Macsec: Macsec SM is in ERROR state. Requires error_clear to recover. May get here due to: - Corrupted 'state' info in RAM - Missing SOP (Got data/eop without SOP) - Missing EOP (Got SOP without EOP) NOTE: While in ERROR state, Macsec forwards data cycles to Crypto ICA HIP as-is.
26:20 Reserved
19   RO 0x0 Depack XTS: CTS Missing indicator: Data needs CTS, but next-to-last indicator was not set.
18   RO 0x0 Depack XTS: CTS Back-2-back Error: next to last and last cycle are not in back2back clock cycles
17   RO 0x0 Depack XTS: Invalid data cycle (key_en, data_en, tweak_en low)
16:15 Reserved
14   RO 0x0 256b egress gasket FIFO 1 overflow
13   RO 0x0 256b egress gasket FIFO 0 overflow
12   RO 0x0 Pack RAM Prefetch UNC ECC NOTE: Recommend to disable this from INT Err PIN & First ERR Log, and use Bit 31 instead.
11   RO 0x0 Depack RAM Prefetch UNC ECC NOTE: Recommend to disable this from INT Err PIN & First ERR Log, and use Bit 28 instead.
10   RO 0x0 256/512 Gasket
9   RO 0x0 Stream RAM UNC ECC
8   RO 0x0 Key RAM UNC ECC
7   RO 0x0 Pack RAM UNC ECC NOTE: Recommend to disable this from INT Err PIN & First ERR Log, and use Bit 31 instead.
6   RO 0x0 Depack RAM UNC ECC NOTE: Recommend to disable this from INT Err PIN & First ERR Log, and use Bit 28 instead.
5   RO 0x0 MAC FIFO UNC ECC
4   RO 0x0 MAC FIFO OVF
3   RO 0x0 AXI ST Egress MST1 FIFO OVF
2   RO 0x0 AXI ST Egress MST0 FIFO OVF
1   RO 0x0 AXI ST Ingress SLV1 FIFO OVF
0   RO 0x0 AXI ST Ingress SLV0 FIFO OVF
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