F-Tile Dynamic Reconfiguration Design Example User Guide

ID 710582
Date 12/19/2022

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Document Table of Contents

5.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example

Figure 29. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example Block Diagram

In the hardware design example, the ISSP modules control the DUT IP reset signals, dr_mode selection and shows the status signals. The hardware test scripts open service to the ISSP to read and drive the values. A JTAG master is instantiated to access the Avalon® memory-mapped interfaces.

The hardware design example executes the dynamic reconfiguration transition process based on user selection as stated in src/parameter.tcl file and checks the DUT IP status, clear the MAC statistics before sending 16 packets, and lastly display the MAC statistics. There is a default dynamic reconfiguration transition sequence, but user can always modify the DR_TRANSITION array variable in src/parameter.tcl file.

DR_TRANSITION: Intended DR sequence array, size of this array variable determines the number of dynamic reconfiguration to be performed. For example, if you want to achieve the following dynamic reconfiguration sequence for 25G-1 Base Variant: Ethernet 25G-1 > CPRI 24G with RSFEC > Ethernet 10G-1, the variables changes are:
set DR_TRANSITION(1) "1x10GE" 

Hardware Flow for Design Example:

The hardware test design <design_example_dir>/hardware_test_design/ directory contains a hwtest subdirectory that contains .tcl script for dynamic reconfiguration hardware testing. Follow the steps shown below to test the design example in hardware.
Figure 30. Hardware Flow for Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example

A successful run displays Test <ftile_ethernet_cpri_dr_test> Passed in the System Console window.

For more information to test the design example in hardware, refer to Testing the Hardware Design Example.