F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 1/07/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 5. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
5. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide

1.3. Directory Structure

The F-Tile Dynamic Reconfiguration design example generates the following files:
Table 4.  Testbench File Descriptions for Design Example
File Names Description
Key Testbench and Simulation Files for CPRI Multirate Designs
<design_example_dir>/example_testbench/basic_avl_tb_top.sv Top-level testbench file. The testbench instantiates the DUT wrapper and runs Verilog HDL tasks to generate and accept packets.
<design_example_dir>/example_testbench/cpriphy_dr_ed_dut_wrapper.sv DUT wrapper that instantiates DUT and other testbench components.
<design_example_dir>/example_testbench/ cpriphy_dr_ed_hw.sv Top hardware design file. This file instantiates the F-Tile Dynamic Reconfiguration Suite Intel FPGA IP, F-Tile Reference and System PLL Clocks Intel FPGA IP, and DUT wrapper.
Key Testbench and Simulation Files for Ethernet Multirate Designs
<design_example_dir>/example_testbench/basic_avl_tb_top.sv Top-level testbench file. The testbench instantiates the DUT wrapper and runs Verilog HDL tasks to generate and accept packets.
<design_example_dir>/example_testbench/ eth_f_hw.sv DUT wrapper that instantiates DUT and other testbench components.
Testbench Scripts
<design_example_dir>/example_testbench/run_vsim.do The ModelSim* SE, Questa* , or Questa*-Intel® FPGA Edition script to run the testbench.
<design_example_dir>/example_testbench/run_vcs.sh The VCS* script to run the testbench.
<design_example_dir>/example_testbench/ run_xcelium.sh The Xcelium* script to run the testbench.
Table 5.  Hardware Design Example File Descriptions
File Names Description
For CPRI Multirate Designs
<design_example_dir>/hardware_test_design/cpriphy_dr_ed_hw.qpf Intel® Quartus® Prime project file.
<design_example_dir>/hardware_test_design/cpriphy_dr_ed_hw.qsf Intel® Quartus® Prime project settings file.
<design_example_dir>/hardware_test_design/cpriphy_dr_ed_hw.sv Top hardware design file. This file instantiates the F-Tile Dynamic Reconfiguration Suite Intel FPGA IP, F-Tile Reference and System PLL Clocks Intel FPGA IP, and DUT wrapper.
<design_example_dir>/hardware_test_design/cpriphy_dr_ed_dut_wrapper.sv DUT wrapper that instantiates DUT and packet client testbench components.
<design_example_dir>/hardware_test_design/cpriphy_dr_ed_hw.sdc Synopsys Design Constraints files. You can copy and modify these files for your own Intel® Agilex™ device.
<design_example_dir>/hardware_test_design/hwtest/main_script.tcl Main file for accessing System Console.
<design_example_dir>/hardware_test_design/hwtest/parameter.tcl Stores the configurable variables of the test script. JTAG ID, desired dynamic reconfiguration sequences of the test can be modified through the variables in this file.
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