F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 1/07/2022
Public

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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 5. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
5. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide

2.1.3. CPRI Multirate Design Example: Reset Scheme

The i_reconfig_reset signal resets the soft registers of CPRI Multirate Intel FPGA IP core and Dynamic Reconfiguration Controller IP. After power up and before starting dynamic reconfiguration sequences, this reset is asserted and released once. This reset must not be asserted afterwards.

The datapath resets, i_rst_n, i_tx_rst_n, and i_rx_rst_n must be asserted when performing the dynamic reconfiguration.

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