F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

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ID 710578
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Related Documentation
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX MII Interface (64b/66b) 2.4. RX MII Interface (64b/66b) 2.5. Status Interface for 64b/66b Line Rate 2.6. TX Interface (8b/10b) 2.7. RX Interface (8b/10b) 2.8. Status Interface for 8b/10b Line Rate 2.9. Serial Interface 2.10. CPRI PHY Reconfiguration Interface 2.11. Datapath Avalon Memory-Mapped Interface 2.12. PMA Avalon Memory-Mapped Interface
2.1. Clock Signals x
2.1.1. Required Clock Frequencies
3. Parameters x
3.1. Sub Profile Parameters Validation
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Dynamic Reconfiguration Settings
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Latency Measurement 5.2. CDR Clock Output 5.3. RX PMA Adaptation
5.1. Latency Measurement x
5.1.1. Deterministic Latency 5.1.2. Calculation for 64b/66b Datapath
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

3.1. Sub Profile Parameters Validation

You must configure the Profile 0 (Power Up profile) using the following parameters before configuring the Sub Profiles:
  • System PLL Frequency
  • CPRI Rate
  • Enable Reconfiguration to 8b/10b Datapath
The F-Tile CPRI PHY Multirate Intel® FPGA IP core validates the dynamic reconfiguration parameters based on the following rules:
  • CPRI rate must be unique among the sub profiles.
  • Maximum number of sub profiles is the number of available lower CPRI rates than the Profile 0 (Power Up profile). Refer to the following table for details.
Table 22.  Sub Profile Availability
Profile 0 (Power Up) Parameter CPRI Rate for Sub Profile (in Gbps)
(64b/66b) (8b/10b)
CPRI Rate

(in Gbps)

Enable Reconfig-uration to 8b/10b Datapath 24.33024 12.16512

with RSFEC

12.16512 10.1376

with RSFEC

10.1376 9.8304 6.144 4.9152 3.072 2.4576 1.2288
24.33024 (64b/66b) with RSFEC On √ √ √ √ √ √ √ √ √ √ √
24.33024 (64b/66b) with RSFEC Off √ √ √ √ √
24.33024 (64b/66b) On √ √ √ √ √ √ √ √ √ √
24.33024 (64b/66b) Off √ √ √ √
12.16512 (64b/66b) with RSFEC On √ √ √ √ √ √ √ √ √
12.16512 (64b/66b) with RSFEC Off √ √ √
12.16512 (64b/66b) On   √ √ √ √ √ √ √ √
12.16512 (64b/66b) Off √ √
10.1376 (64b/66b) with RSFEC On √ √ √ √ √ √ √
10.1376 (64b/66b) with RSFEC Off √
10.1376 (64b/66b) On   √ √ √ √ √ √
10.1376 (64b/66b) Off
9.8304 (8b/10b) Off   √ √ √ √ √
6.144 (8b/10b) Off   √ √ √ √
4.9152 (8b/10b) Off   √ √ √
3.072 (8b/10b) Off   √ √
2.4576 (8b/10b) Off   √
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