F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

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ID 710578
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Related Documentation
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX MII Interface (64b/66b) 2.4. RX MII Interface (64b/66b) 2.5. Status Interface for 64b/66b Line Rate 2.6. TX Interface (8b/10b) 2.7. RX Interface (8b/10b) 2.8. Status Interface for 8b/10b Line Rate 2.9. Serial Interface 2.10. CPRI PHY Reconfiguration Interface 2.11. Datapath Avalon Memory-Mapped Interface 2.12. PMA Avalon Memory-Mapped Interface
2.1. Clock Signals x
2.1.1. Required Clock Frequencies
3. Parameters x
3.1. Sub Profile Parameters Validation
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Dynamic Reconfiguration Settings
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Latency Measurement 5.2. CDR Clock Output 5.3. RX PMA Adaptation
5.1. Latency Measurement x
5.1.1. Deterministic Latency 5.1.2. Calculation for 64b/66b Datapath
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

2.10. CPRI PHY Reconfiguration Interface

Table 18.  CPRI PHY Reconfiguration Interface
Port Name Width (Bits) Domain Description
i_reconfig_cpri_addr[3:0] 4 i_reconfig_clk Address for F-tile CPRI PHY CSRs in the selected channel. Using word addressing format.
i_reconfig_cpri_read 1 i_reconfig_clk Read command for F-tile CPRI PHY CSRs in the selected channel.
i_reconfig_cpri_write 1 i_reconfig_clk Write command for F-tile CPRI PHY CSRs in the selected channel.
o_reconfig_cpri_readdata[31:0] 32 i_reconfig_clk Read data from reads to F-tile CPRI PHY CSRs in the selected channel.
o_reconfig_cpri_readdatavalid 1 i_reconfig_clk Read data from F-tile CPRI PHY CSRs is valid in the selected channel.
i_reconfig_cpri_writedata[31:0] 32 i_reconfig_clk Data for writes to F-tile CPRI PHY CSRs in the selected channel.
o_reconfig_cpri_waitrequest 1 i_reconfig_clk Avalon® memory-mapped interface stalling signal for operations on F-tile CPRI PHY CSRs in the selected channel.
Figure 3. Writing to CPRI PHY Reconfiguration
Figure 4. Reading from CPRI PHY Reconfiguration
Level Two Title