A newer version of this document is available. Customers should click here to go to the newest version.
2.1. Clock Signals
2.2. Reset Signals
2.3. TX MII Interface (64b/66b)
2.4. RX MII Interface (64b/66b)
2.5. Status Interface for 64b/66b Line Rate
2.6. TX Interface (8b/10b)
2.7. RX Interface (8b/10b)
2.8. Status Interface for 8b/10b Line Rate
2.9. Serial Interface
2.10. CPRI PHY Reconfiguration Interface
2.11. Datapath Avalon Memory-Mapped Interface
2.12. PMA Avalon Memory-Mapped Interface
1.4. Device Speed Grade Support
The F-Tile CPRI PHY Intel® FPGA IP core supports Intel® Agilex™ devices with F-tile that have the following speed grade properties:
- Transceiver speed grade: -1 or -2
- Core speed grade: -1 or -2 or -3