F-Tile HDMI Intel® FPGA IP Design Example User Guide

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ID 709314
Date 4/22/2022
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.5.2.1. RX PHY Adapter x
2.5.2.1.1. FRL
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide

2.5.1. HDMI TX Components

The HDMI TX top components include the TX core top-level components, IOPLL, TX PMA Direct PHY, DCFIFO, 40bits to 64bits converter, and the output buffer blocks.
Figure 9. HDMI TX Top Components
Table 10.  HDMI TX Top Components
Module Description
HDMI TX Core

The IP receives video data from the top level and performs auxiliary data encoding, audio data encoding, video data encoding, scrambling, TMDS encoding or packetization.

IOPLL (pll_frl_tx) The IOPLL (pll_frl_tx) generates the FRL clock for the TX core. This reference clock receives the TX FPLL output clock.

FRL clock frequency = Data rate per lanes x 4 / (FRL characters per clock x 18)
IOPLL (pll_cadence_tx) The IOPLL generates the clock for the tx_cadence_slow_clk in the TX transceiver to generate the tx_cadence. Since there is a conversion of the data width from 40bit from TX core to 64 bits in TX transceiver, the tx_cadence_slow_clk needs to be supplied with a clock derived from transceiver output clock with the frequency 5/8*Tx transceiver clock frequency.
TX PMA Direct PHY

Hard transceiver block that receives the parallel data from the HDMI TX core, serializes the data and transmits it.
Output buffer This buffer acts as an interface to interact the I2C interface of the HDMI DDC and redriver components.
40b to 64b Converter Convert 40 bits input to the 64 bits output to be accepted by the transceiver TX.
DCFIFO Synchronize data and signals across the System clock and TX clock domains.
TX Reconfig Management

In TMDS mode, the TX reconfiguration management block reconfigures the TX Transceiver for different output clock frequency according to the TMDS clock frequency of the specific video.

In FRL mode, the TX reconfiguration management block reconfigures the TX Transceiver to supply the serial fast clock for 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps and 12 Gbps according to FRL_Rate field in the 0x31 SCDC register.

The TX reconfiguration management block switches the TX Transceiver reference clock between reference clock 1 for TMDS mode and reference clock 0 for FRL mode.


Section Content
TX PHY Adapter

Level Two Title