F-Tile HDMI Intel® FPGA IP Design Example User Guide

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ID 709314
Date 4/22/2022
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.5.2.1. RX PHY Adapter x
2.5.2.1.1. FRL
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide

1.4. Compiling and Testing the Design

Figure 5. Design Compilation and Hardware Flow
To compile and run a demonstration test on the hardware example design, follow these steps:
  1. Ensure hardware example design generation is complete
  2. Launch the Intel® Quartus® Prime Pro Edition software and open the .qpf file.
    • HDMI 2.1 design example with Support FRL enabled:

      project directory/quartus/agx_hdmi21_frl_demo.qpf

  3. Click Processing > Start Compilation.
  4. After successful compilation, a .sof file generates in your specified directory.
  5. Set up the Hardware and Power up the Intel FPGA board.
  6. Make the necessary clock controller settings. Open the Clock Controller parameter editor and set the clock frequency in Si5391-B tab.
    Note: Based on our user experience on the Clock Controller, user needs to make sure it displays “Connected to the target” before proceeding with the clock settings. If it displays different message, user needs to exit and reopen the Clock Controller. To identify the successful clock settings, F_vco will display a certain clock frequency:
    • Set Out6 frequency to 100.00 Mhz
  7. Configure the selected device on the development board using the generated .sof file (Tools > Programmer).
    • HDMI2.1 design example with Support FRL enabled:
      • project directory/quartus/output_files/agx_hdmi21_frl_demo.sof
  8. If changes are made on the software files, user needs to run the build_sw.sh script to rebuild the software.
  9. Download the software .elf file using the Nios2 Terminal.
    • Download .elf file: nios2-download <project directory> /software/tx_control/tx_control.elf -g -r -i 1
    • Run nios terminal: nios2-terminal -i 1
    Note: Step 9 is an optional step. This step is only needed when user will make changes on the software files.
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