F-Tile HDMI Intel® FPGA IP Design Example User Guide

ID 709314
Date 4/22/2022

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Document Table of Contents

1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices

Updated for:
Intel® Quartus® Prime Design Suite 22.1
IP Version 19.7.0
The HDMI Intel® FPGA IP design example for Intel® Agilex™ F-tile devices features a simulating testbench and a hardware design that supports compilation and hardware testing.
The HDMI Intel® FPGA IP offers the following design examples:
  • HDMI 2.1 Receiver-Transmitter (RX-TX) retransmit design with fixed rate link (FRL) mode enabled
When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Figure 1. Development Stages

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