F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

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ID 709308
Date 10/21/2022
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. Document Revision History for F-Tile DisplayPort Intel FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. Parallel Loopback Design Examples x
2.1. Intel® Agilex™ F-tile DisplayPort SST Parallel Loopback Design Features 2.2. Design Components 2.3. Clocking Scheme 2.4. Interface Signals and Parameters 2.5. Simulation Testbench
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. Document Revision History for F-Tile DisplayPort Intel FPGA IP Design Example User Guide

1.3. Generating the Design

Use the DisplayPort Intel® FPGA IP parameter editor in Intel® Quartus® Prime software to generate the design example.
Figure 3. Generating the Design Flow
  1. Select Tools > IP Catalog, and select Intel® Agilex™ F-tile as the target device family.
    Note: The design example only supports Intel® Agilex™ F-tile devices.
  2. In the IP Catalog, locate and double-click DisplayPort Intel FPGA IP. The New IP Variation window appears.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
  4. Select an Intel® Agilex™ F-tile device in the Device field, or keep the default Intel® Quartus® Prime software device selection.
  5. Click OK. The parameter editor appears.
  6. Configure the desired parameters for both TX and RX.
    Note: The Nios II software has the capability to read and print out the DisplayPort Main Stream Attribute (MSA) information in the Nios II terminal. To read or print the MSA information, turn on the Enable GPU Control parameter.
  7. Under the Design Example tab, select DisplayPort SST Parallel Loopback Without PCR.
  8. Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example. You must select at least one of these options to generate the design example files. If you select both, the generation time becomes longer.
  9. For Target Development Kit, select Intel® Agilex™ I-Series SOC Development Kit. This causes the target device selected in step 4 to change to match the device on the development kit. For Intel® Agilex™ I-Series SOC Development Kit, the default device is AGIB027R31B1E2VR0.
  10. Click Generate Example Design.
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