F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

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ID 709308
Date 10/21/2022
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. Document Revision History for F-Tile DisplayPort Intel FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. Parallel Loopback Design Examples x
2.1. Intel® Agilex™ F-tile DisplayPort SST Parallel Loopback Design Features 2.2. Design Components 2.3. Clocking Scheme 2.4. Interface Signals and Parameters 2.5. Simulation Testbench
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. Document Revision History for F-Tile DisplayPort Intel FPGA IP Design Example User Guide

1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 22.3
IP Version 20.0.1
The DisplayPort Intel® FPGA IP design examples for Intel® Agilex™ F-tile devices feature a simulating testbench and a hardware design that supports compilation and hardware testing.
The DisplayPort Intel® FPGA IP offers the following design examples:
  • DisplayPort SST parallel loopback without a Pixel Clock Recovery (PCR) module
  • DisplayPort SST parallel loopback with AXIS Video Interface

When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.

Figure 1. Development Stages

Section Content
Directory Structure
Hardware and Software Requirements
Generating the Design
Simulating the Design
Compiling and Testing the Design
DisplayPort Intel FPGA IP Design Example Parameters

Related Information
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