AN 942: Signal Tap Tutorial with Design Block Reuse: for Intel® Agilex™ F-Series FPGA Development Board

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ID 709306
Date 12/10/2021
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Core Partition Reuse Debug—Developer 3. Core Partition Reuse Debug—Consumer 4. Root Partition Reuse Debug—Developer 5. Root Partition Reuse Debug—Consumer 6. Document Revision History for AN 942: Signal Tap Tutorial with Design Block Reuse for Intel® Agilex™ F-Series FPGA Development Board
1. Introduction x
1.1. Tutorial Software and Hardware 1.2. Tutorial Files 1.3. Signal Tap with Core Partition Reuse 1.4. Signal Tap with Root Partition Reuse
2. Core Partition Reuse Debug—Developer x
2.1. Step 1: Creating a Core Partition 2.2. Step 2: Creating Partition Boundary Ports 2.3. Step 3: Compiling and Checking Debug Nodes 2.4. Step 4: Exporting the Core Partition and Creating the Black Box File 2.5. Step 5: Copying Files to Consumer Project 2.6. Step 6: Creating a Signal Tap File (Optional) 2.7. Step 7: Programming the Device and Verifying the Hardware 2.8. Step 8: Verifying Hardware with Signal Tap
3. Core Partition Reuse Debug—Consumer x
3.1. Step 1: Adding Files and Running Synthesis 3.2. Step 2: Creating a Signal Tap File 3.3. Step 3: Creating a Partition for blinking_led_top 3.4. Step 4: Compiling the Design and Verifying Debug Nodes 3.5. Step 5: Programming the Device and Verifying the Hardware 3.6. Step 6: Verifying Hardware with Signal Tap
4. Root Partition Reuse Debug—Developer x
4.1. Step 1: Creating a Reserved Core Partition and Defining a Logic Lock Region 4.2. Step 2: Generating and Instantiating SLD JTAG Bridge Agent in the Root Partition 4.3. Step 3: Generating and Instantiating the SLD JTAG Bridge Host 4.4. Step 4: Generating HDL Instance of Signal Tap 4.5. Step 5: Compiling Export Root Partition and Copying Files to Consumer Project 4.6. Step 6: Programming the Device and Verifying the Hardware 4.7. Step 7: Generating a Signal Tap File for the Root Partition 4.8. Step 8: Verifying the Hardware with Signal Tap
5. Root Partition Reuse Debug—Consumer x
5.1. Step 1: Adding Files to Customer Project 5.2. Step 2: Generating and Instantiating SLD JTAG Bridge Host in Reserved Core Partition 5.3. Step 3: Synthesizing, Creating Signal Tap File, and Compiling 5.4. Step 4: Programming the Device and Verifying the Hardware 5.5. Step 5: Verifying the Hardware of Reserved Core Partition with Signal Tap 5.6. Step 6: Verifying Hardware of Root Partition with Signal Tap
1. Introduction
2. Core Partition Reuse Debug—Developer
3. Core Partition Reuse Debug—Consumer
4. Root Partition Reuse Debug—Developer
5. Root Partition Reuse Debug—Consumer
6. Document Revision History for AN 942: Signal Tap Tutorial with Design Block Reuse for Intel® Agilex™ F-Series FPGA Development Board

1.3. Signal Tap with Core Partition Reuse

To perform verification in a reusable core partition, in the Developer project, you must identify the signals of interest, and then make those signals visible to a Signal Tap logic analyzer instance. The Intel® Quartus® Prime software supports two methods of making core partition signals visible for verification:
  • Signal Tap HDL instance—in the Developer project, you create a Signal Tap HDL instance in the reusable core partition and connect the signals of interest to that instance. The Compiler ensures top level visibility of Signal Tap instances inside partitions. Since the root partition and the core partition have separate HDL instances, the Signal Tap files are also separate. The Consumer must generate one Signal Tap file for each HDL instance present in the design,
  • Partition boundary ports—the Developer directly assigns signals as ports to the partition boundary. The top level partition contains an instance of Signal Tap, and signals in the partition boundary connect to it. Assigning boundary ports simplifies the management of hierarchical blocks, by automatically creating ports and tunneling through layers of logic, without making RTL changes. You create partition boundary ports through an Intel® Quartus® Prime Settings File (.qsf) assignment, or with the Assignment Editor. The Developer must include the user created partition boundary ports in the black box file. This action allows the Consumer to tap these ports as pre-synthesis or post-fit nodes.
Figure 3. Consumer Debug Setup with Reused Core Partition

The Consumer can add the Signal Tap logic analyzer to the parent partition with any of these methods:

  • Signal Tap HDL instance
  • Signal Tap GUI to tap pre-synthesis nodes
  • Signal Tap GUI to tap post-fit nodes

In core partition reuse, the Developer creates partition boundary ports with the Assignment Editor, and the Consumer adds pre-synthesis nodes to the parent partition with the Signal Tap GUI.

Figure 4. Tutorial Design Flow for Core Partition Reuse
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