F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 10/15/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.2.8.1. Bonded Lanes Use Case 1

One 100G-4 Ethernet MAC in Ethernet hard IP with PTP enabled

  • Four PMA lanes at 25.78 Gbps per PMA lane
  • Modulation scheme: NRZ
  • Primary streams at EMIB_23
  • One st_x4 fracture is used

One DisplayPort 2.0 in F-tile PMA and FEC Direct PHY IP 5

  • 20.0 Gbps per PMA lane without FEC
  • Dynamic lane scaling from four lanes to two lanes or one lane
  • Modulation scheme: NRZ
  • Primary stream at EMIB_19
  • Four st_x1 fractures are used

One HDMI in F-tile PMA and FEC Direct PHY IP

  • 12.0 Gbps per PMA lane without FEC
  • Modulation scheme: NRZ
  • Primary stream at EMIB_3
  • Four st_x1 fractures are used
Figure 37. Bonded Lanes Use Case 1
5 IP shown for illustrative purposes. Contact Intel FPGA support for specific IP availability.