Quartus® Prime Pro Edition User Guide: Third-party Simulation

ID 683870
Date 3/31/2025
Public

Visible to Intel only — GUID: mwh1410383473101

Ixiasoft

Document Table of Contents

3.2. VCS Guidelines

The following guidelines apply to simulation of Altera FPGA designs in the VCS software:
  • Do not specify the -v option for altera_lnsim.sv because it defines a systemverilog package.
  • Add -verilog and +verilog2001ext+.v options to make sure all .v files are compiled as verilog 2001 files, and all other files are compiled as systemverilog files.
  • Add the -lca option for Stratix® V and later families because they include IEEE-encrypted simulation files for VCS.
  • Add -timescale=1ps/1ps to ensure picosecond resolution.
Note: Starting in version 25.1, the "VCS MX" tool flow is now referred to as the "VCS (3-step) flow" which is fully supported. The “VCS” tool flow is now referred to as “VCS (2-step) flow" which is also supported but is deprecated.