Quartus® Prime Pro Edition User Guide: Third-party Simulation
ID
683870
Date
3/31/2025
Public
Answers to Top FAQs
1. FPGA Simulation Basics
2. Siemens EDA QuestaSim* Simulator Support
3. Synopsys VCS* Support
4. Aldec Active-HDL and Riviera-PRO Support
5. Cadence Xcelium* Parallel Simulator Support
6. Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Quartus® Prime Pro Edition User Guides
1.1. FPGA Simulation Essential Elements
1.2. Overview of Simulation Tool Flow
1.3. Simulation Tool Flow
1.4. Supported Simulation Flows
1.5. Supported Hardware Description Languages
1.6. Supported Simulation Types
1.7. Supported Simulators
1.8. Post-Fit Simulation Support by FPGA Family
1.9. Automating Simulation with the Run Simulation Feature
1.10. Using Precompiled Simulation Libraries
1.11. FPGA Simulation Basics Revision History
1.9.3.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode)
1.9.3.2. Optional Simulation Settings for Run Simulation (Batch Mode)
1.9.3.3. Launching Simulation with the Run Simulation Feature
1.9.3.4. Running RTL Simulation using Run Simulation
1.9.3.5. Output Directories and Files for Run Simulation
1.3.2.2. Order of Files for Compilation Commands
The order of files that you specify to compilation commands is irrelevant for Verilog and SystemVerilog files in many instances. The main exception is when there are files defining SystemVerilog packages, or other files that import or otherwise refer to those SystemVerilog packages.
Important: You must compile the files defining the SystemVerilog packages before compiling the files that import or refer to those packages. Otherwise, the compilation command errors out when compiling files that import or refer to those SystemVerilog packages.
For example, suppose file multp_pkg.sv defines the SystemVerilog package multp, and the file my_design.sv imports package multp:
- If you compile both multp_pkg.sv and my_design.sv with a single compilation command, you must ensure that multp_pkg.sv occurs before my_design.sv.
- If you compile multp_pkg.sv and my_design.sv using separate compilation commands, you must ensure that you run the command that is compiling multp_pkg.sv first.
VHDL has stricter requirements for ordering the files. For example, when a VHDL file foo.vhd refers to a logical library name lib1, you must compile the files into lib1 first, before compiling foo.vhd into another library.