Quartus® Prime Pro Edition User Guide: Third-party Simulation
ID
683870
Date
3/31/2025
Public
Answers to Top FAQs
1. FPGA Simulation Basics
2. Siemens EDA QuestaSim* Simulator Support
3. Synopsys VCS* Support
4. Aldec Active-HDL and Riviera-PRO Support
5. Cadence Xcelium* Parallel Simulator Support
6. Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Quartus® Prime Pro Edition User Guides
1.1. FPGA Simulation Essential Elements
1.2. Overview of Simulation Tool Flow
1.3. Simulation Tool Flow
1.4. Supported Simulation Flows
1.5. Supported Hardware Description Languages
1.6. Supported Simulation Types
1.7. Supported Simulators
1.8. Post-Fit Simulation Support by FPGA Family
1.9. Automating Simulation with the Run Simulation Feature
1.10. Using Precompiled Simulation Libraries
1.11. FPGA Simulation Basics Revision History
1.9.3.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode)
1.9.3.2. Optional Simulation Settings for Run Simulation (Batch Mode)
1.9.3.3. Launching Simulation with the Run Simulation Feature
1.9.3.4. Running RTL Simulation using Run Simulation
1.9.3.5. Output Directories and Files for Run Simulation
1.3.3.4. Finding Logical Library Names in Simulation Library Compiler Output
After you generate the simulation script using the Simulation Library Compiler, you may need to inspect the script to identify the logical library names for use with your elaboration command (vsim).
To identify the logical library names for Quartus® Prime simulation libraries in the generated script, search for all of the lines that begin with vmap, such as the following line:
vmap altera_ver "./verilog_libs/altera_ver"
The first argument to vmap is the logical library name (altera_ver). The second argument is the physical directory where the library content is stored. This second argument is irrelevant for Questa*-Intel® FPGA Edition because you do not run the command.