E-Tile Hard IP Agilex™ 7 Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 4/30/2024
Document Table of Contents Generating New HEX File Using Eclipse-based Ashling RiscFree IDE Tool

Use Eclipse-based Ashling Riscfree IDE tool to generate HEX file instead of running the script generate_hex_script.sh.
  1. In the <design_example_dir>/software/dynamic_reconfiguration_sim folder, execute the following commands:
    • Execute the command niosv-bsp -c --quartus-project=../../hardware_test_design/alt_ehipc3.qpf --qsys=../../hardware_test_design/nios_system.qsys --type=hal etile_dr_cpu_bsp/settings.bsp to generate the BSP files.
    • Execute the command niosv-app --bsp-dir=etile_dr_cpu_bsp --app-dir=etile_dr_cpu_app --srcs=. --elfname=etile_dr_cpu.elf to generate the user application CMakeLists.txt.
  2. Run the Eclipse-based Ashling Riscfree IDE Tool launcher.
  3. Create a new workspace when the Workspace Launcher window prompt appears.
  4. Click Launch to open the workspace.
  5. In the Eclipse-based Ashling Riscfree IDE Tool window, select File > New > Project. A New Project window appears.
  6. Choose C/C++ > C/C++ Project > C++ Managed Build.
    • For the Project name, specify your desired project name. This example uses dynamic_reconfiguration_simulation.
    • For project type, select CMake driven > Empty Project. For Toolchains, select CMake driven.
    • Click Finish. The CMake driven application is added to the Project Explorer.
    • Uncheck Use default location. Navigate to <example_design_dir>/software/dynamic_reconfiguration_sim/etile_dr_cpu_app to locate the CMakeLists.txt in the NIOS V application project.
  7. On the Project Explorer view, right-click the project and select Build Project. Ensure the etile_dr_cpu.elf file is generated in the <design_example_dir>/software/dynamic_reconfiguration_sim/etile_dr_cpu_app/build/Debug directory.
  8. Do the following to generate a Hex file:
    • Go to <design_example_dir>/software/ dynamic_reconfiguration_sim.
    • Run the command elf2hex etile_dr_cpu_app/build/Debug/etile_dr_cpu.elf -o nios_system_oc_mem2_0 _onchip_memory2_0.hex -b 0x04000000 -r 4 -w 32 -e 0x0407ffff.

Follow these steps to simulate the testbench:

  1. Open the <simulator_name>_files.tcl script in the <design_example_dir>/example_testbench/setup_scripts/common directory.
  2. Edit the TCL script to change the existing nios_system_oc_mem2_0_onchip_memory2_0.hex file directory to the new HEX file generated from the Eclipse-based Ashling RiscFree IDE Tool.
    For example, change the following line in the TCL script from:
    lappend memory_files "[normalize_path "$QSYS_SIMDIR/../<design_example_dir>/hardware_test_design/ip/nios_system/nios_system_oc_mem2_0/altera_avalon_onchip_memory2_191/sim/nios_system_oc_mem2_0_onchip_memory2_0.hex"]"
    lappend memory_files "[normalize_path "$QSYS_SIMDIR/../<design_example_dir>/hardware_test_design/software/dynamic_reconfiguration_sim/nios_system_oc_mem2_0_onchip_memory2_0.hex"]"
  3. Using the supported simulator of your choice, change to the testbench simulation directory to <design_example_dir>/example_testbench/ <simulator_name>.
  4. Run the simulation script for the simulator. The script compiles and runs the testbench in the simulator. Refer to the Steps to Simulate the Testbench table.
  5. Analyze the results. The successful testbench performs the DR operations, sends and transmits packets for each DR operation, and displays "Nios has completed its transactions" and "Simulation PASSED" after completing the simulation.
    Note: For Nios® V-based testbench, the simulation runs for more than 5 hours.