E-Tile Hard IP Agilex™ 7 Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 4/30/2024
Public
Document Table of Contents

4.2.1.1. Clocking Scheme

Figure 32. Clocking Scheme for 10G/25GE MAC+PCS with RS-FEC and PTP Dynamic Reconfiguration Design Example
Figure 33. Clocking Scheme for 10G/25GE MAC+PCS with RS-FEC Dynamic Reconfiguration Design Example
Note: i_channel_PLL module is E-tile Transceiver PHY specific module that utilizes additional transceiver E-tile channel.