2.2. Core Cache Interface (CCI-P) Interface
| Parameter | Value | Notes |
|---|---|---|
| Width | 512-bit | CCI-P interface width. |
| Maximum CCI-P Frequency | pClk | - |
| Host Memory Cache-Line Size | 64-byte | - |
| Minimal write access size | 1-byte | AFUs can write 1 byte to 63 bytes by setting the mode of TX channel 1 to a value of 1'b1 |
| MMIO access width | 32-bit and 64-bit | 64-bit accesses are mandatory for Device Feature Header (DFH) enumeration. |
| MMIO Read Response Timeout | 65536 clock cycles | - |
| Virtual Channels Supported | VH0, VA | Accesses to VH0 and VA are mapped to the PCIe* link. Accesses to VH1 or VL0 are mapped to VH0. |