FPGA Interface Manager Data Sheet: Intel FPGA Programmable Acceleration Card D5005

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ID 683858
Date 8/18/2021
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. FIM and AFU Parameter Data 3. FPGA Interface Manager (FIM) Resource Utilization 4. Document Revision History for FPGA Interface Manager Data Sheet: Intel FPGA Programmable Acceleration Card D5005
2. FIM and AFU Parameter Data x
2.1. Memory Interface 2.2. Core Cache Interface (CCI-P) Interface 2.3. Clocks 2.4. Reset 2.5. Networking Interface
2.1. Memory Interface x
2.1.1. SDRAM Signals
2.5. Networking Interface x
2.5.1. Clock Signals 2.5.2. Data Interface and Signals 2.5.3. Control and Status Signals
1. Overview
2. FIM and AFU Parameter Data
3. FPGA Interface Manager (FIM) Resource Utilization
4. Document Revision History for FPGA Interface Manager Data Sheet: Intel FPGA Programmable Acceleration Card D5005

4. Document Revision History for FPGA Interface Manager Data Sheet: Intel FPGA Programmable Acceleration Card D5005

Document Version Acceleration Stack Version Changes
2021.08.18 2.0.1 Clarified description in section: SDRAM Signals.
2020.06.03 2.0.1 Added the Address Mapping parameter in Table: Local Memory Interface Specifications.
2020.03.26 2.0.1
Updated:
  • Maximum burst size row in Local Memory Interface Specifications Table in Memory Interface
  • readdata and writedata rows in SDRAM Interface Table in SDRAM Signals
2020.02.10 2.0.1 Increased the value of AFU-accessible memory Data Width to add the ECC bits.
2019.11.04 2.0.1 Initial Release
Level Two Title