2.3. Clocks

FPGA Interface Manager Data Sheet: Intel FPGA Programmable Acceleration Card D5005

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ID 683858

Date 8/18/2021

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2.3. Clocks

Table 4. Clock Specifications
Parameter	Value	Notes
`pClk`	250 MHz	Primary interface clock. All CCI-P interface signals are synchronous to this clock.
`pClkDiv2`	125 MHz	Synchronous and in phase with `pClk`. 0.5x the `pClk` clock frequency.
`pClkDiv4`	62.5 MHz	Synchronous and in phase with `pClk`. 0.25x the `pClk` clock frequency.
`uClk_usr Min`	10 MHz	Minimum user-defined clock. This clock is not synchronous with the `pClk`. You can adjust this clock using OPAE.
`uClk_usr Default`	312.5 MHz	Default user-defined clock. This clock is not synchronous with the `pClk`. You can adjust this clock using OPAE.
`uClk_usr Max`	600 MHz	Maximum user-defined clock. This clock is not synchronous with the `pClk`. You can adjust this clock using OPAE.
`uClk_usrDiv2 Min`	10 MHz	Minimum user defined clock that is synchronous with `uClk_usr` and 0.5x the frequency. Note: You can use OPAE to set the frequency to be a value other than half the `uClk_usr` frequency.
`uClk_usrDiv2 Default`	156.25 MHz	User defined clock that is synchronous with `uClk_usr` and 0.5x the frequency. Note: You can use OPAE to set the frequency to be a value other than half the `uClk_usr` frequency.
`uClk_usrDiv2 Max`	600 MHz	Maximum user defined clock that is synchronous with `uClk_usr` and 0.5x the frequency. Note: You can use OPAE to set the frequency to be a value other than half the `uClk_usr` frequency.