FPGA Interface Manager Data Sheet: Intel FPGA Programmable Acceleration Card D5005

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ID 683858
Date 8/18/2021
Public

1. Overview

The FPGA Interface Manager (FIM) data sheet provides the key parameters to which you must design your Accelerator Functional Unit (AFU).
The FIM consists of the following:
  • FPGA Interface Unit (FIU): The platform interface layer that acts as a bridge between PCIe* and Core Cache Interface (CCI-P).
  • Core Cache Interface (CCI-P): standard interface AFUs use to communicate with the host.
  • External Memory Interface (EMIF)
  • High-Speed Serial Interface (HSSI) for external transceivers
Each of these components have parameter values that must be met by the AFU.
Figure 1.  Intel® FPGA PAC D5005
Level Two Title