Design in the Intel® MAX® 10 Device
Block | Description |
---|---|
Nios® II Processor | The soft processor manages the operation of the design. The Nios® II E core is used in this design example. |
PLL | Synthesizes the clocks required in this design example. PLL output counter C0—to synthesize 80-MHz clock for the whole system. |
Timer | This design example uses a 1-minute timer. By default, the system checks for voltages and temperature at every 5-minutes interval. If the voltage or temperature exceeds the preset limits, the Nios® II processor will data log the value to the UFM. You can change the timer interval value (TIMER_MINUTE) in main.h. You can also change the timer minute using the UPDATE_TIMER command. |
On-Chip RAM | Storage for the program memory. |
TSD | The TSD measures the temperature on the Intel® MAX® 10 device. The presets are defined in main.h. You can also preset on-the-fly using the TEMP command when connected to a PC through the UART. The fan speed is based on the threshold temperature in the system. |
PWM | This is a custom Platform Designer component. The duty cycle of the PWM is used to control the fan speed. For more information about this custom component, refer to the PWM Registers and Setting table. |
System fan |
The default value for the low threshold is 20°C and the high threshold is 50°C. You can set the threshold value using the TEMP command.
You can change the duty cycle and the PWM frequency in fan.c. When the board is powered on, the fan runs at 33.33% duty cycle. After each timer interrupts, the program reads the TSD temperature and tune the fan to operate at a different speed. You can change the fan speed to 1, 2, or 3 using the FAN command. |
ADC | You can send command to read the voltage and temperature of each channel. There are up to 16 analog inputs that are muxed to the Intel® MAX® 10 ADC. This enables the Intel® MAX® 10 device to monitor multiple voltage rails in the system. |
UFM | Storage for data logs—failing channel, failing voltage, or failing temperature. Data is stored based on their failing condition. Two types of data are stored in UFM1.
Where Y is the failing channel or group, XXX is the 12-bit output data produced by the ADC or TSD block. LED3 is turned on when UFM1 is full. No new data log will be written into UFM1 when it is full. When UFM1 is full, you need to read all the UFM1 data to the PC. You can save the readout to a file on the PC for analysis if required. After that, you need to erase the UFM before new data can be logged into the UFM again. You can also perform some basic functions by using Erase UFM1, Read UFM1, and Check UFM1 Space commands. |
PMBus | The PMBus is built using the OpenCores IP and is used to control the external power module. The PMBus is a standard protocol used in power management applications. It is built on top of the I2C with additional ALERT and CONTROL lines. In this design example, the SCL, SDA, and ALERT pins must be pulled to high using a 1-kΩ resistor to run at 400 kHz. This design example supports the following commands:
You can add new commands in power.c and power.h. |
UART | Interactive terminal. The list of supported commands in this design example is listed in the Supported Commands table. You can add your command by modifying main.c. |
Register Name | Size (Bits) | Address (Binary) | Setting | R/W |
---|---|---|---|---|
Period | 32 | 0 | Specify the PWM period, in clock cycles. | R/W |
Pulse | 32 | 1 | Specify the duration of the high pulse of the PWM, in clock cycles. | R/W |