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2.3. Simulation Design Example
The eCPRI design example generates a simulation testbench and simulation files that instantiates the eCPRI Intel® FPGA IP core when you select the Simulation or Synthesis & Simulation option.
Figure 8. eCPRI Intel® FPGA IP Simulation Block Diagram
Note: The Nios II Subsystem block is not present in the design example generated for Intel® Arria® 10 and Intel® Agilex™ F-tile devices.In this design example, the simulation testbench provides basic functionality such as startup and wait for lock, transmit and receive packets.
The successful test run displays output confirming the following behavior:
- The client logic resets the IP core.
- The client logic waits for the RX datapath alignment.
- The client logic transmits packets on the Avalon-ST interface.
- Receive and checks for the content and correctness of the packets.
- Display "Test PASSED" message.
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