eCPRI Intel® FPGA IP Design Example User Guide

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ID 683837
Date 11/15/2022
Public

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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. eCPRI Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for eCPRI Intel® FPGA IP Design Example User Guide A. Generating and Downloading the Executable and Linking Format (.elf) Programming File
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the eCPRI Intel FPGA IP Design Example
1.4. Simulating the Design Example Testbench x
1.4.1. Enabling Dynamic Reconfiguration to the Ethernet IP
2. Design Example Description x
2.1. Features 2.2. Hardware Design Example 2.3. Simulation Design Example 2.4. Interface Signals 2.5. Design Example Register Map
1. Quick Start Guide
2. Design Example Description
3. eCPRI Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for eCPRI Intel® FPGA IP Design Example User Guide
A. Generating and Downloading the Executable and Linking Format (.elf) Programming File

2.1. Features

  • Internal TX and RX serial loopback mode
  • Automatically generates fixed size packets
  • Basic packet checking capabilities
  • Ability to use System Console to test the design and reset the design for re-testing purpose
Level Two Title

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