AN 500: NAND Flash Memory Interface with Altera MAX Series

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ID 683829
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. NAND Flash Memory Interface with Altera MAX Series
1. NAND Flash Memory Interface with Altera MAX Series x
1.1. NAND Flash Interface Using Altera Devices 1.2. Implementation 1.3. Acknowledgments 1.4. Document Revision History
1.1. NAND Flash Interface Using Altera Devices x
1.1.1. Signals 1.1.2. Operations 1.1.3. AMD and Samsung NAND Flash Devices Commands
1.2. Implementation x
1.2.1. Source Code
1. NAND Flash Memory Interface with Altera MAX Series

1.1.2. Operations

Each operation performed is coded in a different format and issues through the 3-bit wide control bus.

Table 2.  Operations Performed by the Interface on Different Combinations of the Control Signals
Control Signal [2:0] EN/DB# Operation performed
000 — Command Latch Enabled (CLE = 1) irrespective of the condition on EN/DB#.
001 — Read Data / status / device depend on the command sent on the I/O lines.
010 — Write Data / command /address depending on the command sent on the I/O lines.
011

1

0

ALE is asserted (high).

ALE is disabled (low).

100

1

0

SE# is asserted (low).

SE# is disabled (high).

Note: This operation is only applicable for AMD flash devices. This command enables/disables the 16 bytes of spare area on each page depending on the condition of the EN/DB# line.
101

1

0

WP# is asserted (low).

WP# is disabled (high).

110

1

0

CE# is asserted (low).

CE# is disabled (high).

111

1

0

The status of the flash device is sent on the RY/BY# line.

RY/BY# line does not reflect the status of the flash device.

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