AN 500: NAND Flash Memory Interface with Altera MAX Series

ID 683829
Date 9/22/2014
Public

1.1. NAND Flash Interface Using Altera Devices

The commands from the system arrive at the inputs of the NAND Flash interface in coded form. Each operation performed is coded in a different format and issues through the 3-bit wide control bus.

Enabling or disabling (in the case of ALE, CLE, SE, and WE) is done separately with the help of enable/disable signal inputs. These commands are decoded correctly by the NAND Flash interface block (of the supported Altera devices) and translated as output enabling or disabling signals, which ensures the desired operation of the NAND Flash.

The actual operation performed by a NAND Flash is governed by the commands written into its command register through the I/O bus. The address of the data that is read or written, together with the data, are issued through the same bus.

Figure 1. Interfacing Signals of the NAND Flash DeviceThis figure shows host interfacing signals and NAND Flash device interfacing signals. The signals followed by a # are asserted when low.

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