AN 818: Static Update Partial Reconfiguration Tutorial: for Intel® Stratix® 10 GX FPGA Development Board

ID 683826
Date 5/12/2021
Public

1.5.3. Step 3: Allocate Placement and Routing Regions

For every base revision that you create, the Compiler uses the PR partition region allocation to place the corresponding persona core in the reserved region. Follow these steps to locate and assign a PR region in the device floorplan for your base revision:
  1. In the Project Navigator Hierarchy tab, right-click the u_blinking_led instance, and then click Logic Lock Region > Create New Logic Lock Region. The region appears in the Logic Lock Regions window.
  2. Specify a region Width of 5 and Height of 5.
  3. Specify the placement region coordinates for u_blinking_led in the Origin column. The origin corresponds to the lower-left corner of the region. Specify the Origin as X184_Y420. The Compiler calculates (X188 Y424) as the top-right coordinate.
  4. Enable the Reserved and Core-Only options for the region.
  5. Double-click the Routing Region option. The Logic Lock Routing Region Settings dialog box appears.
  6. For the Routing Type, select Fixed with expansion. This option automatically assigns an Expansion length of one.
  7. Repeat the previous steps to allocate the following resources for the u_top_counter partition:
    • Height5
    • Width5
    • OriginX191_Y420
    • Routing RegionFixed with expansion with Expansion length of one.
    • ReservedOn
    • Core-OnlyOn
    Note: The routing region must be larger than the placement region, to provide extra flexibility for the Compiler's routing stage, when the Compiler routes different personas.
  8. Your placement region must enclose the blinking_led logic. To select the placement region by locating the node in Chip Planner, right-click the u_blinking_led region name in the Logic Lock Regions window, and then click Locate Node > Locate in Chip Planner.
  9. Under Partition Reports, double-click Report Design Partitions. The Chip Planner highlights and color codes the region.
    Figure 6. Chip Planner Node Location for blinking_led

    Alternatively, adding the following lines to blinking_led.qsf creates these regions:

    set_instance_assignment -name PARTITION supr_partition -to u_top_counter
    set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON -to \
         u_top_counter
    
    set_instance_assignment -name PLACE_REGION "X191 Y420 X195 Y424" -to \
         u_top_counter
    set_instance_assignment -name RESERVE_PLACE_REGION ON -to u_top_counter
    set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to u_top_counter
    set_instance_assignment -name ROUTE_REGION "X190 Y419 X196 Y425" -to \
         u_top_counter
    
    set_instance_assignment -name PARTITION pr_partition -to u_blinking_led
    set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON -to \
         u_blinking_led
    set_instance_assignment -name RESERVE_PLACE_REGION_ON -to u_blinking_led
    set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to \
         u_blinking_led
    set_instance_assignment -name PLACE_REGION "X184 Y420 X188 Y424" \
         -to u_blinking_led
    set_instance_assignment -name ROUTE_REGION "X183 Y419 X189 Y425" \
         -to u_blinking_led

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