AN 818: Static Update Partial Reconfiguration Tutorial: for Intel® Stratix® 10 GX FPGA Development Board

ID 683826
Date 5/12/2021

1.2. Reference Design Overview

This reference design consists of one, 32-bit counter. At the board level, the design connects the clock to a 50MHz source, and then connects the output to four LEDs on the board. Selecting the output from the counter bits, in a specific sequence, causes the LEDs to blink at a specific frequency. The top_counter module is the SUPR region.
Figure 1. Flat Reference Design