AN 818: Static Update Partial Reconfiguration Tutorial: for Intel® Stratix® 10 GX FPGA Development Board

Download PDF
ID 683826
Date 5/12/2021
Public
Document Table of Contents
Document Table of Contents x
1. Static Update Partial Reconfiguration Tutorial for Intel® Stratix® 10 GX FPGA Development Board
1. Static Update Partial Reconfiguration Tutorial for Intel® Stratix® 10 GX FPGA Development Board x
1.1. Tutorial Requirements 1.2. Reference Design Overview 1.3. Static Update Region Overview 1.4. Download Reference Design Files 1.5. Reference Design Walkthrough 1.6. Static Update Partial Reconfiguration Tutorial Revision History
1.5. Reference Design Walkthrough x
1.5.1. Step 1: Getting Started 1.5.2. Step 2: Create Design Partitions 1.5.3. Step 3: Allocate Placement and Routing Regions 1.5.4. Step 4: Define Personas 1.5.5. Step 5: Create Revisions 1.5.6. Step 6: Compile the Base Revision 1.5.7. Step 7: Set Up PR Implementation Revisions 1.5.8. Step 8: Change the SUPR Logic 1.5.9. Step 9: Program the Board 1.5.10. Modifying the SUPR Partition
1.5.5. Step 5: Create Revisions x
1.5.5.1. Setting the Base Revision 1.5.5.2. Creating Implementation Revisions
1.5.9. Step 9: Program the Board x
1.5.9.1. Troubleshooting PR Programming Errors
1. Static Update Partial Reconfiguration Tutorial for Intel® Stratix® 10 GX FPGA Development Board

1.5.1. Step 1: Getting Started

To copy the reference design files to your working environment and compile the blinking_led flat design:
  1. Before you begin, Download Reference Design Files.
  2. Create the s10_pcie_devkit_blinking_led_supr directory in your working environment.
  3. Copy the downloaded tutorials/s10_pcie_devkit_blinking_led/flat sub-folder to the s10_pcie_devkit_blinking_led_supr directory.
  4. In the Intel® Quartus® Prime Pro Edition software, click File > Open Project and open /flat/blinking_led.qpf.
  5. To compile the base design, click Processing > Start Compilation. The Timing Analyzer reports open automatically when compilation is complete. You can close the Timing Analyzer for now.
Level Two Title