Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 2/11/2023

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Document Table of Contents

3.1. Multi Channel DMA

Multi Channel DMA IP for PCI Express consists primarily of H2DDM & D2HDM blocks. It also offers a DMA-bypass capability to the Host for doing PIO Read/Writes to device memory.

The MCDMA engine operates on software DMA queue to transfer data between local FPGA and host. The elements of each queue are software descriptors that are written by driver/software. Hardware reads the queue descriptors and executes them. Hardware can support up to 2K DMA channels. For each channel, separate queues are used for read/write DMA operations.

Note: MCDMA requires the Source and Destination addresses be 64 byte aligned in D2H direction. This may not be required in future release.