Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 2/11/2023

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4.5. Bursting Avalon-MM Master (BAM) Interface

Table 44.  BAM Signals
Signal Name I/O Type Description
bam_address_o[<n>:0] Output Represents a byte address. The value of address must align to the data width. <n>: {vfactive+$clog2(PF_NUM)+11+3+BAR_addr_width}-1, where vfactive=1, PF_NUM=number of PFs enabled, 11=$clog2(2048), 3=bar_num width, BAR_addr_width= 22 bits (H-Tile) / max(BAR_addr_width) (P-Tile and F-Tile and R-Tile)

x16: bam_byteenable_o[63:0]

x8: bam_byteenable_o[31:0]


Enables one or more specify the valid bytes of write data during transfer on interfaces. For x16, each bas_bytenable bit correspond to a byte in bam_writedata_o[511:0].

For single-cycle read bursts and for all write bursts, all contiguous sets of enabled bytes are supported.

For multi-cycle read bursts, all bits of bam_byteenable_o[63:0] are asserted, regardless of the First Byte Enable (BE) and Last BE fields of the corresponding TLP.

x16: bam_burstcount_o[3:0]

x8: bam_burstcount_o[4:0]

Output Used by a bursting master to indicate the number of transfers in each burst.
bam_read_o Output Asserted to indicate a read transfer.

x16: bam_readdata_i[511:0]

x8: bam_readdata_i[255:0]

Input Read data from the user logic in response to a read transfer
bam_readdatavalid_i Input When asserted, indicates that the bam_readdata signal contains valid data in response to a previous read request. For a read burst with burstcount value <n>, the readdatavalid signal must be asserted <n> times, once for each readdata item.
bam_write_o Output Asserted to indicate a write transfer

x16: bam_writedata_o[511:0]

x8: bam_writedata_o[255:0]

Output Data for write transfers
bam_waitrequest_i Input

When asserted, indicates that the Avalon-MM slave is not ready to respond to a request.

WaitrequestAllowance is upto 16 cycle.