Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 2/11/2023

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Document Table of Contents

1.2. Known Issues

The following summarizes known issues in the current IP release:
  1. MCDMA AVMM PIO may drop Posted Writes when user logic backpressures by asserting rx_pio_waitrequest_i
  2. Multichannel D2H AVST configuration has stability issues when total number of D2H channels configured is greater than 256
  3. Per vector masking capability for MSI-X is not supported in MCDMA IP Intel® Quartus® Prime 22.4.
  4. Design Example simulation in Intel® Quartus® Prime 22.4 release is failing for BAM+BAS+MCDMA user mode in H-Tile, when SRIOV is enabled.
  5. R-Tile MCDMA Design Example simulations are not supported in Intel® Quartus® Prime 22.4 release.
  6. MCDMA IP may have CPL-Reordering issues in BAS & MCDMA user modes, if 10-bit tag capability is enabled and MCDMA IP auto negotiated to 8-bit tag only. This applies to P-Tile, F-Tile and R-Tile MCDMA IP in Intel® Quartus® Prime 22.4 release.
  7. Avalon-ST Source (H2D) interface data can get corrupted, if a Completion timeout event occurrs for H2DDM descriptor fetch. This issue happens only if the SOP descriptor is fetched successfully and the EOP descriptor for a channel got missed because of the Completion timeout event.
  8. Low D2H throughput is observed with Ubuntu 22.04. A fix may be implemented in a future release.
Note: These issues may be addressed in a future release of Intel® Quartus® Prime software.