Generic Nios II Booting Methods User Guide

ID 683820
Date 5/24/2016

1.1. Overview

Altera® Nios® II processor is a soft processor that supports all Altera System on Chip (SoC) and Field Programmable Gate Array (FPGA) families. Developing Nios II embedded programs can be based on Altera hardware abstraction layer (HAL). The creation and management of software projects based on the HAL is integrated tightly with the Nios II Software Build Tools (SBT).

The boot memory could be the Compact Flash Interface (CFI) flash, User Flash Memory (UFM) flash, Altera Serial Flash (EPCS)/Altera Quad Serial Flash (EPCQ) configuration device or on-chip RAM (OCRAM). Regardless of the nature of the boot memory, HAL-based systems are constructed so that the reset vector and all program and data sections are initially stored in the boot memory. The HAL provides a small boot loader program (also known as boot copier) that copies these sections to their run time location at boot time. You can specify the run time locations for program and data memory by manipulating the Nios II BSP settings.

This document describes:
  • The Nios II processor boot copier that boots your Nios II system according to the boot memory selection
  • Nios II processor booting options and general flow
  • Nios II programming solutions for selected boot memory