Serial Lite III Streaming Intel® FPGA IP Core Release Notes

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ID 683807
Date 4/08/2024
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1. Serial Lite III Streaming Intel FPGA IP Core Release Notes
1. Serial Lite III Streaming Intel FPGA IP Core Release Notes x
1.1. Serial Lite III Streaming Intel FPGA IP Core v20.1.0 1.2. Serial Lite III Streaming Intel FPGA IP Core v20.0.2 1.3. Serial Lite III Streaming Intel FPGA IP Core v20.0.1 1.4. Serial Lite III Streaming Intel FPGA IP Core v20.0 1.5. Serial Lite III Streaming Intel FPGA IP Core v18.1 1.6. SerialLite III Streaming Intel FPGA IP Core v18.0 1.7. Intel FPGA SerialLite III Streaming IP Core v17.1 1.8. SerialLite III Streaming IP Core v17.0 1.9. SerialLite III Streaming IP Core v16.1 1.10. SerialLite III Streaming IP Core v16.0 1.11. SerialLite III Streaming IP Core v15.1 1.12. SerialLite III Streaming IP Core v15.0 1.13. SerialLite III Streaming IP Core v14.1
1. Serial Lite III Streaming Intel FPGA IP Core Release Notes

1.11. SerialLite III Streaming IP Core v15.1

Table 11.  v15.1 November 2015
Description Impact
Added a new parameter—Burst Gap. —
For Arria 10 devices, the PMA width for Interlaken mode is changed to 64 bits. IP Upgrade is compulsory if you are using Arria 10 devices.

For Arria 10 devices, automatic upgrade will fail for IP core that uses Standard Clocking mode and was generated in a prior version of the Quartus II software. You must uncheck the Auto Upgrade option and click Upgrade in Editor to select a valid Transceiver Reference Clock frequency if the existing selection is invalid.

For Stratix V and Arria V GZ devices, these changes are optional. If you do not upgrade your IP core, it does not have these new features.

For Arria 10 devices, the I/O PLL replaces the fractional PLL (fPLL) in generating the core clock and user clock signals.
Updated the bit function in the error_tx signal.
Updated the design example to support Arria 10 devices.
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